-- $Id: $
-- File name:   tb_RCU.vhd
-- Created:     10/12/2010
-- Author:      Christopher Sakalis
-- Lab Section: 4
-- Version:     1.0  Initial Test Bench

library ieee;
--library gold_lib;   --UNCOMMENT if you're using a GOLD model
use ieee.std_logic_1164.all;
--use gold_lib.all;   --UNCOMMENT if you're using a GOLD model

entity tb_RCU is
generic (Period : Time := 83.34 ns);
end tb_RCU;

architecture TEST of tb_RCU is

  function INT_TO_STD_LOGIC( X: INTEGER; NumBits: INTEGER )
     return STD_LOGIC_VECTOR is
    variable RES : STD_LOGIC_VECTOR(NumBits-1 downto 0);
    variable tmp : INTEGER;
  begin
    tmp := X;
    for i in 0 to NumBits-1 loop
      if (tmp mod 2)=1 then
        res(i) := '1';
      else
        res(i) := '0';
      end if;
      tmp := tmp/2;
    end loop;
    return res;
  end;

  component RCU
    PORT(
         CLK : in std_logic;
         RST_N : in std_logic;
         D_EDGE : in std_logic;
         EOP : in std_logic;
         SHIFT_ENABLE : in std_logic;
         RCV_DATA : in std_logic_vector (7 downto 0);
         RCVING : out std_logic;
         W_ENABLE : out std_logic;
         R_ERROR : out std_logic
    );
  end component;

-- Insert signals Declarations here
  signal CLK : std_logic;
  signal RST_N : std_logic;
  signal D_EDGE : std_logic;
  signal EOP : std_logic;
  signal SHIFT_ENABLE : std_logic;
  signal RCV_DATA : std_logic_vector (7 downto 0);
  signal RCVING : std_logic;
  signal W_ENABLE : std_logic;
  signal R_ERROR : std_logic;

-- signal <name> : <type>;

begin

CLKGEN: process
  variable CLK_tmp: std_logic := '0';
begin
  CLK_tmp := not CLK_tmp;
  CLK <= CLK_tmp;
  wait for Period/2;
end process;

  DUT: RCU port map(
                CLK => CLK,
                RST_N => RST_N,
                D_EDGE => D_EDGE,
                EOP => EOP,
                SHIFT_ENABLE => SHIFT_ENABLE,
                RCV_DATA => RCV_DATA,
                RCVING => RCVING,
                W_ENABLE => W_ENABLE,
                R_ERROR => R_ERROR
                );

--   GOLD: <GOLD_NAME> port map(<put mappings here>);

process

  begin

-- Insert TEST BENCH Code Here

--     RST_N <= 
--     D_EDGE <= 
--     EOP <= 
--     SHIFT_ENABLE <= 
--     RCV_DATA <= 

     RST_N <= '1';
     D_EDGE <= '0';
     EOP <= '0';
     SHIFT_ENABLE <= '0';
     RCV_DATA <= "00000000";

     wait for period;
     RST_N <= '0';
     wait for period;
     RST_N <= '1';


--?????????????????????????
     wait for period;
     D_EDGE <= '1';
     wait for period;
     D_EDGE <= '0';
     wait for period;
--      wait for period;


     SHIFT_ENABLE <='1';
     wait for period;
     SHIFT_ENABLE <='0';

     wait for period;
     wait for period;
     wait for period;
     SHIFT_ENABLE <='1';
     wait for period;
     SHIFT_ENABLE <='0';

     wait for period;
     SHIFT_ENABLE <='1';
     wait for period;
     SHIFT_ENABLE <='0';

     wait for period;
     SHIFT_ENABLE <='1';
     wait for period;
     SHIFT_ENABLE <='0';

     wait for period;
     EOP <= '1';
     wait for period;
     EOP <= '0';

     wait for period;
     EOP <= '1';
     wait for period;
     EOP <= '0';

--????????????????????????
     wait for period;
     D_EDGE <= '1';
     wait for period;
     D_EDGE <= '0';


     wait for period;
     SHIFT_ENABLE <='1';
     wait for period;
     SHIFT_ENABLE <='0';

     wait for period;
     SHIFT_ENABLE <='1';
     wait for period;
     SHIFT_ENABLE <='0';

     wait for period;
     wait for period;
     wait for period;

     wait for period;
     SHIFT_ENABLE <='1';
     wait for period;
     SHIFT_ENABLE <='0';

     wait for period;
     SHIFT_ENABLE <='1';
     wait for period;
     SHIFT_ENABLE <='0';

     wait for period;
     SHIFT_ENABLE <='1';
     wait for period;
     SHIFT_ENABLE <='0';

     wait for period;
     SHIFT_ENABLE <='1';
     wait for period;
     SHIFT_ENABLE <='0';

     RCV_DATA <= "10000000";

     wait for period;
     SHIFT_ENABLE <='1';
     wait for period;
     SHIFT_ENABLE <='0';

     wait for period;
     SHIFT_ENABLE <='1';
     wait for period;
     SHIFT_ENABLE <='0';

--?????????????????????????

--Test for when STRT=0:

     wait for period;
     SHIFT_ENABLE <='1';
     wait for period;
     SHIFT_ENABLE <='0';

--Cpunt again up to 8:

     wait for period;
     SHIFT_ENABLE <='1';
     wait for period;
     SHIFT_ENABLE <='0';

     wait for period;
     SHIFT_ENABLE <='1';
     wait for period;
     SHIFT_ENABLE <='0';

     wait for period;
     SHIFT_ENABLE <='1';
     wait for period;
     SHIFT_ENABLE <='0';

     wait for period;
     SHIFT_ENABLE <='1';
     wait for period;
     SHIFT_ENABLE <='0';

     wait for period;
     SHIFT_ENABLE <='1';
     wait for period;
     SHIFT_ENABLE <='0';

     wait for period;
     SHIFT_ENABLE <='1';
     wait for period;
     SHIFT_ENABLE <='0';

     wait for period;
     SHIFT_ENABLE <='1';
     wait for period;
     SHIFT_ENABLE <='0';

     wait for period;
     SHIFT_ENABLE <='1';
     wait for period;
     SHIFT_ENABLE <='0';


     wait for period;
     wait for period;
     wait for period;
     wait for period;
     wait for period;



     wait for period;
     SHIFT_ENABLE <='1';
     wait for period;
     SHIFT_ENABLE <='0';


     wait for period;
     wait for period;
     SHIFT_ENABLE <='1';
     wait for period;
     SHIFT_ENABLE <='0';


     wait for period;
     wait for period;
     wait for period;
     SHIFT_ENABLE <='1';
     wait for period;
     SHIFT_ENABLE <='0';


     wait for 20*period;

     EOP <='1';
     wait for period;
     wait for period;
     SHIFT_ENABLE <='1';
     wait for period;
     SHIFT_ENABLE <='0';

     wait for period;
     SHIFT_ENABLE <='1';
     wait for period;
     SHIFT_ENABLE <='0';


     wait for period;
     wait for period;
     wait for period;
     D_EDGE <= '1';
     wait for period;
     D_EDGE <= '0';

     wait for period;
     wait for period;
     wait for period;
     RST_N <= '0';
     wait for period;
     RST_N <= '1';
     wait for period;

     EOP <='0';
     wait for period;
     SHIFT_ENABLE <='1';
     wait for period;
     SHIFT_ENABLE <='0';

     wait for period;
     SHIFT_ENABLE <='1';
     wait for period;
     SHIFT_ENABLE <='0';

     wait for period;
     SHIFT_ENABLE <='1';
     wait for period;
     SHIFT_ENABLE <='0';



     wait for period;
     wait for period;
     D_EDGE <= '1';
     wait for period;
     D_EDGE <= '0';


     wait for period;
     SHIFT_ENABLE <='1';
     wait for period;
     SHIFT_ENABLE <='0';

     wait for period;
     SHIFT_ENABLE <='1';
     wait for period;
     SHIFT_ENABLE <='0';


     wait for period;
     EOP <='1';
     wait for period;
     EOP <='0';


      wait for 10*period;
      D_EDGE <= '1';
      wait for period;
      D_EDGE <= '0';


--      wait for 10*period;
--      EOP <='1';
--      wait for period;
--      EOP <='0';




------------------------------
     --wait for 80 ns;
-- --      SHIFT_ENABLE <='1';
-- --      wait for 80 ns;
-- -- 
-- --      D_EDGE <= '1';
-- --      wait for 80 ns;
-- -- 
-- --      D_EDGE <= '0';
-- --      wait for 80 ns;
-- -- 
-- --      RCV_DATA <= "00000100";
-- --      wait for 80 ns;
-- --      RCV_DATA <= "00000001";
-- --      wait for 80 ns;
-- --      RCV_DATA <= "00000010";
-- --      wait for 80 ns;
-- --      RCV_DATA <= "00000011";
-- --      wait for 80 ns;
-- --      RCV_DATA <= "10000000";
-- --      wait for 80 ns;
-- -- 
-- -- --??????????????
-- -- --??????????????
-- -- --??????????????
-- -- --??????????????
-- --      wait for 1420 ns;
-- --      EOP <= '1';
-- -- 
-- --      wait for period;
-- --      EOP <= '0';
-- -- 
-- --      wait for period;
-- --      D_EDGE <= '1';
-- --      wait for 80 ns;
-- -- 
-- --      D_EDGE <= '0';
-- --      wait for 80 ns;
-- -- 
-- --      wait for period;
-- --      RCV_DATA <= "10000000";
-- --      wait for 1000 ns;
-- -- 
-- --      RCV_DATA <= "11110000";
-- --      wait for 80 ns;
-- -- --??????????????
-- -- --??????????????
-- -- 
-- --      --wait for 4700 ns;
-- --      wait for 5000 ns;
-- --      EOP <= '1';
-- -- 
      wait;


  end process;
end TEST;














